Quick start

This is the shortest path from a released SD-card image to a validated DE10-Nano and a first digital output.

Version note: this manual follows the current source tree and can be newer than the latest published binary image. Check the selected release notes for its included commands. If a documented command is missing, use documentation from that release or deploy a matching current-source build.

The example-led User manual targets current main and host/FPGA ABI 6. Follow those chapters only with a matching host build and FPGA image.

What you need

  • a DE10-Nano with its power supply
  • a microSD card and card reader
  • Ethernet access, or a USB mini cable for the UART console
  • optionally, an oscilloscope or logic analyzer for observing the first output

No shield or external wiring is required for the baseline self-test.

1. Download and flash the image

Download the latest binary SD-card image from the PulsePins releases page.

Write the image to the microSD card with a tool such as BalenaEtcher, Raspberry Pi Imager, or Rufus. Insert the card into the DE10-Nano before applying power.

2. Boot and find the board

Connect Ethernet and power on the board. The released image requests an address using DHCP. Its default Ethernet MAC address is D6:7D:AE:B3:0E:BA.

Find the assigned address in your router's DHCP lease list. If Ethernet is unavailable, connect through the USB mini port marked UART; the hardware setup page covers the fallback path and board-access details.

3. Log in

Connect over SSH, substituting the board's address:

ssh root@BOARD_IP

The released image initially uses:

  • user: root
  • password: eit

Change the default password before placing the board on an untrusted network:

passwd

You can also install your public SSH key with ssh-copy-id root@BOARD_IP from your development machine.

4. Validate the baseline image

Disconnect external circuits from the PulsePins output, valid, and strobe pins, or first verify that they can safely accept generated 3.3 V patterns. The self-tests enable the output drivers and exercise nonzero values even though they do not require external loopback wiring.

On the board, run:

run_all_tests

The command should exit successfully and print SUCCESS. At the default 100 MHz streamer clock, a full run currently takes about seven minutes. It uses the FPGA readback path for internal comparison.

If the check fails, keep the complete output and continue with Testing procedures.

5. Generate a first output

PulsePins uses 3.3 V LVTTL signals. Disconnect equipment that must not be driven, then use the DE10-Nano signal reference or the PP_PMOD hardware reference to connect qout[0] and ground to a high-impedance scope or logic-analyzer input. Do not apply a direct 50 ohm termination to an unbuffered FPGA pin.

Generate ten 10 ms periods on qout[0], returning the bus to zero afterward:

ppfg -burst 10 -period 10ms -trig -v1 0x1 -v0 0x0 -t 0x0

Expect ten 50% duty-cycle pulses on qout[0]; the other output bits remain low. ppfg can return to the shell before the hardware burst finishes, so observe the complete ten-period burst rather than treating the prompt as completion. The final value is zero, but the output drivers remain enabled. Follow the manual cleanup before connecting another driver.

Optional burn-in

For a longer board check, run:

run_all_tests_forever

The runner stops at the first failed sweep. Current-source builds write summary and per-run logs under /var/volatile/pulsepins-test-logs; older images may differ. See Testing procedures for current log details and reporting options.

Where to go next